For the technology beyond the 22-nm node CMOS, the use of compressively strained germanium (Ge) as a channel material attracts much interest for the pMOS FinFET. Although Ge material has a higher intrinsic hole mobility than Si, relaxed Ge channel devices do not outperform strained Si channel p-FINFETs. Strained Ge is crucial to boost channel mobility.
Since the 90-nm technology, embedded SiGe source/drain has been used as a stressor in Si pMOS devices. However, with scaling down to sub-22 nm nodes, much less space will limit the source and drain and this stress technique becomes less efficient.
This resulted in a renewed interest in stress formation in Ge channels by SiGe strain relaxed buffers (SRBs) epitaxially grown on Si. The scheme becomes challenging as downscaling goes together with a reduction in thickness of the shallow trench isolation (STI), which in turn sets a limit on the thickness of the SiGe SRB in the case where the Si in between the STI oxide is recessed and replaced by the SiGe SRB.
When trying to implement compressively strained Ge channels on SiGe strain relaxed buffers, a variety of problems exist for the technology beyond the 22-nm node CMOS.
For instance, fabricating a large relaxation degree (>85%) of strain-relaxed Si1-xGex (for instance with x>0.7) is difficult because the thickness of the shallow trench isolation (STI) sets a limit to the thickness of the Si1-xGex SRB. If the SiGe SRB is not strongly (>85%) or fully relaxed, there is an increased risk for strain relaxation of the strained germanium channel, and for an increased leakage current of the final devices. Moreover, if the SiGe is not sufficiently relaxed, further relaxation might occur during subsequent process steps. This would lead to process unreliability, as there might be a higher wafer-to-wafer variation and the final degree of relaxation might vary as function of device dimensions.
In addition, for future technology nodes, the STI thickness is further reduced, which also reduces the maximal allowable Si1-xGex thickness. This makes the fabrication of SiGe SRBs extremely challenging. Strain relaxation only happens above a certain critical thickness. For a given layer thickness, the driving force for further relaxation reduces with increasing degree of relaxation. In conventional schemes, a high degree of strain relaxation is achieved by making the semiconductor layer sufficiently thick. Techniques to make relative thin strain relaxed buffers, in general rely on the controlled implementation of material imperfections (defects) to initiate strain relaxation. However, the presence of defects needs to be avoided/minimised as it has a detrimental effect on final device performance.
Moreover, initiation of layer relaxation comes together with the formation of misfit dislocations. On (001) surfaces, a misfit dislocation network is formed which extends up to 50 nm above the SiGe-SRB/Si-substrate interface which sets a minimum thickness on the SiGe SRB layer to keep the Ge surface channel out of this defective area. If the SiGe has a 50 nm thick defective layer, it limits the minimum thickness of SiGe to keep the Ge channel out of this defective area. Indeed, if a Ge channel layer is grown on such a defective SiGe buffer, the defects can extend to Ge channel layer and thus relax the Ge layer.
Also, due to the formation of facets (e.g. {111} and/or {311} facets, but not limited thereto) during the selective epitaxial growth, the Ge content is not uniform in Si1-xGex (for instance with x>0.7) SRBs, which results in the non-uniformity of strain distribution in the Ge channel layer. In addition, the top surface of the Si1-xGex (for instance x>0.7) SRB may be rounded and not flat, which would also result in an unwanted rounded surface of Ge channel layer.
It is difficult to grow a fully compressively strained Ge channel layer on top of Si1-xGex SRBs, and there exists a need in industry for such solutions.